The invention relates to an electronic apparatus comprising stations capable of communicating via a bus conductor. The invention also relates to a station for use in such an electronic apparatus.
Such an electronic apparatus is known from the commercially available I2C bus system described in the "Data Handbook IC20: 80C51-based 8-bit microcontrollers" issued by Philips Semiconductors in 1994, pages 1141-1159.
The I2C bus uses two bus conductors: a clocksignal conductor (SCL) carrying a clocksignal and a datasignal conductor (SDA) carrying a datasignal. Message transfer via the I2C bus requires the stations to participate in various operations according to a signal protocol.
In the I2C protocol a master station controls the potential of the clock signal conductor, but other stations which participate in communication can delay clockpulses. This allows the other stations to take as much time as needed for handling the data. To delay the clock pulses the stations are capable of establishing the potential of the clock signal conductor via a wired logic function. That is, the clocks signal conductor is connected to a load circuit for pulling the clock signal conductor to a quiescent potential level when none of the stations drives the clock signal conductor against the load circuit. The stations contain wired logic drive circuits for driving the potential of the clock signal conductor against the load circuit.
In the I2C bus the stations are similarly connected on a wired logic basis to the data signal conductor. In case of the data signal conductor, the wired logic is used to make it possible that different stations attempt at the same time to supply their address to the data signal conductor during arbitration; the wired logic is also used to allow different directions of communication after arbitration.
When none of the stations drives the bus conductor against the load circuit, the potential of the bus conductor changes towards the quiescent level with a speed which is determined by a current supplied to the bus conductor by the load circuit. As published in the Data Handbook IC20, in an embodiment of the I2C bus the load circuit contains a resistor which pulls the potential of the bus conductor to the quiescent level from the moment that the last station stops driving the potential of the bus conductor against the load circuit.
In addition the load circuit of this embodiment of the I2C bus contains an additional current source which starts supplying additional current to the bus conductor once the resistor has pulled the potential of the bus conductor to within a threshold of the quiescent level. The additional current speeds up the change of potential level of the bus conductor at a time when the current through the resistor decreases.
The additional current source in this embodiment is off at the moment that the last station stops driving the potential of the bus conductor against the load circuit and for a time interval thereafter. This is because the I2C bus specifies a maximum current that may be supplied to the bus conductor at any one time to pull it towards the quiescent level. This specification ensures that the bus conductor may be driven against the load circuit at any time by a wired logic drive circuit with a specified drive strength.
Although this maximum imposed on the current is unavoidable if one wants to communicate with stations satisfying the I2C standard, the maximum current specified for the I2C bus is a drawback because it limits the speed of potential level changes on the bus conductors and thereby the maximum speed of message transfer.